Most modern day dynamic random access memory (DRAM) devices use a well known set of circuits in an array of memory cells to sense a small charge from a chosen memory cell. The charge is amplified to a much larger, full-rail voltage on a pair of digit lines. Such circuitry, called sense amplifiers, essentially function as enabled flip-flops. A well known enhancement of the basic sense amplifier is the addition of isolation gates between the digit lines and n-channel sense amplifier devices. Such isolation gates, referred to as ISO gates, resistively shelter the digit line capacitance from the n-sense amplifier, and thus allow the sense amplifier to sense and latch the correct data much more quickly. To read and write a particular digit line pair, a decoded Y-gate is then turned on, coupling the digit line pair to an I/O line pair.
A variety of techniques are used to amplify the data once the I/O line pair is coupled to the digit line pair. Earlier designs used circuits coupled to the I/O lines that were identical to the digit line sense amplifiers. Such circuits were termed helper flip-flops, and functioned by sensing, amplifying and then latching the I/O line data.
Newer techniques perform this function by resistively tying both I/O lines to the power supply voltage to provide a DC bias current, and then allowing the digit line sense amplifier to pull one of the I/O lines to a lower level. The I/O lines are thus not latched or driven by any additional circuits, except for the digit line sense amplifiers. Such techniques avoid the timing problems associated with helper flip-flop techniques, such as the possibility of trying to sense and latch too early, and thus irreversibly latching wrong data on the I/O line.
One feature of this technique is that DC current flows from the power supply voltage, through the bias devices, through the Y-gate, through the ISO gates, and finally through the n-sense amplifier device to ground. This DC current allows one of the I/O lines to resistively divide down to a lower voltage, but unfortunately also allows the low digit line to pull up to a voltage higher than ground. When a row access signal (RAS) is taken high to deactivate the DRAM, the Y-gate is turned off, and the low digit line decays to a ground potential through the n-sense amplifier. It is undesirable to decouple the memory cell from the digit line by shutting off the row line until the low digit line has decayed to an acceptable low level to avoid writing incorrect data back into the memory cell.
As DRAM densities increase, the digit line capacitance grows due to longer digit lines as well as tighter spacing. Additionally, the resistance of the ISO device increases to provide further protection for the n-sense amplifier. Hence, the RC time constant that determines the decay time becomes larger, and can be so long as to adversely affect the overall speed grade of the DRAM.
There is therefore a need to return the low digit line to a ground potential as quickly as possible once the DRAM is deactivated. There is a further need to do this with as little circuitry as possible, since chip area is at a premium.